J. C. Tsang*, J. A. Kash* and D. P. Vallett+
* IBM Research Division
Yorktown Heights, NY 10598
+ IBM
Microelectronics Division
Essex Junction, VT 05452
Modern laser and electro-optic techniques can generate images in the visible with a spatial resolution of better than 0.1mm, and measure changes in light intensity with a temporal resolution of a fraction of a picosecond. Such capabilities are now needed for the test, debug, and failure analysis of modern silicon integrated circuits (ICs).[1] The complexity of modern ICs means that many different kinds of physical errors can occur. These need to be identified and fixed before a new chip is ready for the marketplace. Being able to carry through this process promptly by the optical methods discussed in this note is now an important enabler of Moore’s law.
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| Figure 1. A schematic view of a flip chip packaged IC showing that only the substrate side ("back side") of the package is physically accessible for studies of the device layer of the chip when it is normally working through the solder ball contacts made to the "front side" of the chip. (based on Figure 1 of Ref 1.) |
The physical characteristics and projected performance of CMOS ICs in the next decade can be obtained from the latest edition of the Semiconductor Industry Association’s “International Technology Roadmap for Semiconductors.”[2] This document presents critical target parameters for future ICs, including minimum device dimensions and spacings between devices, clock speeds, acceptable clock jitter and skew, etc. Two developments highlighted in the roadmap are driving the need for optical techniques to measure switching and timing characteristics of new chips. These factors are the large number of dense metal layers which now cover the “ front” or device side of the chip, and the use of “ flip-chip” packaging techniques. (Figure 1) Each of these severely limits direct physical access to the transistors and low level wiring between transistors. Direct physical access is now possible only by removal of portions of the metal wiring layers, or by drilling holes through the substrate. Such disassembly of a finished part can introduce new errors, degrade chip performance, and is usually time consuming. As a result, optical tools working at photon energies near or below the bandgap of silicon where the substrate of the chip is at least partially transparent now have substantial advantages over traditional tools such as mechanical probes or electron beams for measuring electrical activity in a chip. In order to be useful in measuring the electrical activity in normally packaged, fully functional integrated circuits, the tools must employ light at wavelengths near 1mm to identify devices on the 0.1mm spatial scale, measure voltage changes of the order of 1V, and do so with a temporal resolution of better than 10 psec.
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| Figure 2. A schematic of the bandstructure od Si showing the optical transitions that can contribute to either hot carrier light emission (large downward arrows), or to the modulation of the reflectivity due to the carriers and voltages associated with device activity in FETs (small upward arrows).(based on Figure 2 of Ref 1.) |
Because of its indirect band gap, silicon has not been used for lasers and found only limited applications in optoelectronics. Nonetheless, it, it has well defined optoelectronic properties, which allowed the recent development of two practical optical methods to monitor the electrical activity in silicon field effect transistors (FETs) from the backside of a chip. The first technique, Picosecond Imaging Circuit Analysis(PICA), uses the light emitted by FETs while in saturation. Each time a CMOS circuit switches logic state, the FETs are briefly in saturation and a weak picosecond light pulse is emitted. The light emission process involves intraconduction or intravalence band processes; the interband processes responsible for electrically excited light emission in direct gap III-V and II-VI materials are too weak to be useful in Si. The second technique uses a near-band-gap picosecond laser which is synchronized to the chip clock as a probe to measure changes in reflectivity from an FET; the reflectance is modified by the local charge density and by the application of voltages across an interface, especially at a p-n junction. This technique, known as Laser Voltage Probing (LVP) requires careful measurement of light reflected from a junction in an IC and can be used to determine changes in voltage across the junction with picosecond temporal resolution.[3] The transitions involved in each of these processes are shown schematically in Fig. 2 In either case, the time dependent signal (light emission or reflected intensity) describes the time variation of the voltages across the device being observed.
In the case of PICA, there is very weak light emission whenever a CMOS logic gate in the IC switches states. During a switching transition, current exists in the FETs of the gate, and for a brief instant, one of the FETs is in saturation. The combination of the current, and the high fields near the drain of FETs in saturation results in a pulse of intraband hot carrier light emission, as indicated in Figure 3. The intensity of the hot carrier light emission is very weak. In general, for currently available IC technologies and detectors, only one photon is detected for every 105 to 106 switching events. Reasonable signal to noise ratios require summation over billions of switching events. Fortunately, summing such a large number of events is not difficult in the era of 100-1000 MHz ICs(Figure 4). For the solution of practical problems in modern ICs, the current implementation of the PICA technique uses commercially available imaging photomultiplers, and can require measurements lasting minutes to hours depending on duty cycle. The use of imaging photodetectors however means that thousands of devices can be observed during a single measurement, which mitigates the often long data acquisition time.
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| Figure 3. A schematic of the temporal relationship of the current and voltage across a CMOS inverter during switching, and the hot carrier light emission from the nFET and the pFET of the inverter. Light from the nFET and the pFET is observed in sequence as the inverter switches state and most of the supply voltage is first dropped across the nFET and then the pFET. (Figure 4 of Ref 1.) |
Time resolution in PICA is obtained from the time correlated photon counting technique; the full width at half maximum of present systems is less than 100 psec. On the other hand, the temporal duration of the light emission is a small fraction of the gate-to-gate delay. For example, for logic gates where this delay is about 10 psec, the light emission will have a width of less than 5 psec. In spite of this mismatch, the present measuring technique provides adequate signal-noise to identify time shifts of emission peaks on the 5 psec scale. A side benefit of the simultaneous spatial and temporal measurement in the PICA technique is that FETs separated by less than the diffraction limit of conventional optics can often be separated because the emission occurs at distinct, non-overlapping times.
For the LVP method, the modulation of an incident laser beam by the switching of a gate in a CMOS IC can produce a change in the amplitude of the reflected light of as small as 1:106. This reflectance change can arise from either the voltages across a junction in the gate or by changes in the charge density with the electronic state of the gate.[3] To obtain detectable signals, the laser photon energy is close to the silicon band edge, so that the reflectance change is resonantly enhanced. However, the signal-to-noise cannot be increased by increasing the intensity of the probe beam because at higher intensities, the probe can inject enough carriers into a device to perturb device performance. Because of the small size of the modulation, single waveform acquisitions typically take 5-15 minutes, in addition to the time required to carefully aim the laser at a spot on the FET which provides adequate reflectance modulation. The signal-to-noise also depends on the overlap between the size of the laser probe, and the device being measured. For device sizes below 0.5 microns, the 1mm laser wavelength means that the signal level will be degraded by a mismatch between the laser spot size and the device size. Another issue for LVP concerns the time resolution: the picosecond probe laser must be synchronized to the output of the electrical tester driving the chip. While passively mode-locked lasers are capable of sub-picosecond pulse widths, current methods for synching a mode-locked laser to the operating frequency of an IC limits the temporal resolution of LVPs to 20-50 psec.[4]. Finally, in the new generation of silicon on insulator chips, the reflection from the insulating layer and the overall shallow active regions substantially limit detectable reflectance changes, so that LVP may not work at all with these chips.
Both PICA and LVP are being used today to localize faults and defects in ICs.[1,5] Both techniques would benefit from advances in laser and electro-optic technology especially with regards to improvements in sensitivity, and temporal resolution. For PICA, its use today with imaging photomultipliers based on photocathodes with relatively poor (<0.5%) response at wavelengths > 0.9mm, means that only a tiny fraction of the IR photons generated by the hot carriers at energies below the Si band gap are detected. This limited IR sensitivity is a major reason for the integration times required at present. The use of improved IR sensitive photocathodes could produce substantial improvements in the time required for measurements. Also, the use of time correlated photon counting systems with existing photomultiplers for temporally resolving the light emission means that the instrumental resolution is considerably poorer than the optical pulse widths. It has been demonstrated that photodetectors such as specially thinned silicon Single Photon Avalanche Diodes (SPADs) can observe the PICA emission with a instrumental full-width-at-half-maximum of about 30 psec, much closer to the actual linewidths of the emission.[6] However, the thin avalanche region of the diode necessary for the fast response time limits the efficiency of the detector to the near IR photons. As single channel devices, they also cannot compete with the efficiency of imaging detectors which can observe many thousands of devices in a single measurement. Low noise, fast multi-element SPADs based on materials with smaller bandgaps that silicon would be very useful for PICA. The creation of efficient upconversion methods appropriate to the broad spectrum of the PICA emission could also significantly expand PICA’s capabilities, as these upconversion techniques can have temporal resolution of less than 1 psec .
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| Figure 4. Time resolved light emission images from a CMOS microprocessor during the operation of the clock tree of the chip at several different instants of time. The four images show that different parts of the chip are active and emit light at different times. (Figure 11 of Ref 1.) |
Useful improvements in the performance of LVP can also be expected through advances in the laser and electro-optic tool kit. The ability to synchronize a mode locked laser to an external trigger over the range of frequencies characteristic of modern ICs with a pulse width of the order of 10 psec would be desirable. The need of LVP to be able to focus an optical probe on a single device, or part of a single device, hundreds of microns below the surface of the sample, where the device spacings are less than 0.5mm and probe wavelength are greater than 1mm, emphasizes the need to use advanced imaging techniques such as solid immersion lenses. Improvements in this technology including the fabrication of the lenses and technology for the scanning of such lenses would provide many benefits to LVP.
Both PICA and LVP are being deployed today by advanced IC manufacturers, and we have noted in the previous paragraph how the techniques could be further improved. The ongoing need of the IC industry for optical tools that can cope with CMOS parts which are flip-chip packaged presents significant opportunities for scientifically interesting, and technically fruitful research collaborations.
References:
[1] J. C. Tsang, J. A. Kash and D. P. Vallett, “ Time-resolved optical characterization of electrical activity in integrated circuits,” Proceedings of the IEEE 85, 1440-1459 (2000).
[2] “ International technology roadmap for semiconductors: 1999 edition,” Semiconductor Industry Association. (on line at SIA http://www.itrs.net/1999_ SIA_Roadmap/Home.htm)
[3] H. Heinrich, “ Picosecond non-invasive optical detection of internal electrical signals in flip-chip-mounted silicon integrated circuits,” IBM J. Res. and Develop. 34, 162-172 (1990)
[4] S. Kasapi, C. C. Tsao, K. Wilsher, W. Lo, and S. Somani, “ Baser beam backside probing of CMOS integrated circuits,” Microelectronics Reliability 39, 957-961 (1999).
[5] P. Song, F. Motika, D. R. Knebel, R. F. Rizzolo, and M. P. Kusko, “ S/390 G5 CMOS microprocessor diagnostics,” IBM J. Res. And Develop. 43, 899-913 (1999).
[6] F. Stellari (private communication).