J. D. SCHAUB¹, D. L. ROGERS¹, M. YANG¹, S. M. CSUTAK², B. YANG³, J. C. CAMPBELL³

¹IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 (914) 945-2984, schaubj@us.ibm.com
²Applied Optoelectronics Inc., Sugar Land, TX 77478
³Microelectronics Research Center, The University of Texas, Austin, Texas 78712

Introduction

Microprocessor clock speeds continue to increase and high-end computer systems require advanced levels of integration with multiple processors per board to attain higher performance. Within 5 years, high-speed computer backplanes with data rates of 5-6Gb/s will be limited to lengths of 75cm using copper interconnections [1]. At these speeds, optical interconnects offer an attractive alternative in terms of density, power dissipation and cost, especially for rack-to-rack connections with length requirements of up to 10m. Future high-speed backplanes at higher data rates would similarly benefit from an optical solution.

While long distance optical fiber links are optimized at wavelengths of 1.3mm or 1.55mm to take advantage of the low dispersion and low attenuation minima of optical fiber, dispersion and attenuation become negligible at short distances and it becomes cost effective to utilize multimode fiber and low-cost vertical cavity surface emitting laser (VCSEL) technology based at 0.85mm.

In the past, optical receivers have typically been designed using a column III-V photodetector, typically with an absorption region of GaAs or In_(x)Ga_(1-x)As, and an amplifier fabricated in silicon CMOS or SiGe HBT technology. Using this methodology, the photodetector and the amplifier are optimized separately, and the devices are packaged together with wirebonds after fabrication. This approach has several drawbacks when designing arrays. First, it is costly and complex to wirebond an array of photodiodes to an array of amplifiers. Second, at high speeds the performance is degraded by packaging parasitics such as wirebond inductance and bonding pad capacitance. Electrical crosstalk between channels is exacerbated by wirebond leads. One alternative is the use of flip-chip technology to attach the chips, eliminating the wirebond step. However, this approach poses significant manufacturing challenges in terms of alignment and reliability due to thermal mismatch.

An alternate approach is to take advantage of the low cost, high reliability and volume manufacturability inherent to silicon technology by monolithically integrating a silicon-based photodiode with a silicon amplifier. This approach offers considerable challenges as well. Due to the indirect bandgap of silicon, absorption of 850nm light is a relatively inefficient process (Figure 1). The absorption length in silicon is almost 20mm compared to 1.1mm for GaAs. One can imagine the difficulty in trying to fit a thick (many micron) structure into the silicon CMOS process, which is optimized for very thin films on the order of 100nm. The long absorption length also causes problems in achieving high bandwidths at low operating voltages. Until recently, the performance of silicon optical receivers has lagged behind hybrid counterparts. This article outlines recent advances in high performance silicon-based photodiodes and monolithic silicon optical receivers. We discuss the prospects for receiver arrays based on advanced Si CMOS and SiGe HBT technology and review recent demonstrations of high-speed (5-11Gb/s) silicon optical receivers.

Silicon optical receiver design

Figure 1. Absorption coefficient of GaAs and Si as a function of wavelength.

Optimum photodetector design requires an understanding of the performance requirements of the optical receiver. The most important measure of optical receiver performance is the sensitivity, P, defined as the minimum optical power incident on the photodiode at which the receiver can achieve a certain signal-to-noise ratio. For example, an optical receiver that complies with the 850nm 10Gb/s Ethernet standard must achieve a signal to noise ratio of 7.0, equivalent to a bit error ratio (BER) of 10^-12, at an average optical power of 38.5mW, or -14.1dBm [2]. The sensitivity depends on the equivalent noise current at the input of the amplifier, as described by the classical theory [3]. The dominant noise terms in a common source CMOS receiver are the thermal noise from the feedback

Figure 2. Ideal sensitivity of silicon receivers based on CMOS and HBT technology. These calculations assume a photodiode capacitance of 0.25pF and a feedback resistance of 400W, typical values for a 10Gb/s design.

resistor and the channel noise of the input FET. The dominant noise terms in a common emitter bipolar receiver include the thermal noise from the feedback resistor along with the shot noise from the collector current. Ideal sensitivity calculations for a receiver designed in advanced silicon CMOS or SiGe HBT technology is shown in Figure 2. A photodetector with a moderate external quantum efficiency of 30% can achieve a BER of 10^-12 at 10Gb/s at an optical power of -15.5dBm in CMOS and -17.4dBm in SiGe HBT technology. This leaves ample margin for short distance interconnects where optical power is not in short supply. The critical challenge is to design a high-speed, low-voltage, low capacitance and moderate quantum efficiency photodetector that is compatible with standard silicon fabrication processes.

Silicon photodetector structures

The most common photodiode structure is the vertical PIN device. One way to realize this structure in a silicon process is by using the base-collector-subcollector junction in a bipolar transistor [4]. The absorption length of this design is limited to roughly 1mm due to the impact on the performance of the transistor, and this limits the achievable quantum efficiency. It is difficult to achieve both high bandwidth and high efficiency with a vertical design since the length of the absorption region is proportional to the carrier transit time.

Vertical silicon photodiodes have also been reported with metal-semiconductor-metal (MSM) structures. Typically, these offer high speed (pulsewidth=6.7ps) but suffer from low quantum efficiency (4.6%) [5], although a bandwidth of 82GHz and efficiency of 19% was achieved on a vertical MSM device with backside texturing [6]. These devices feature a buried Schottky metal under a thin (<400nm) absorption region, which would be difficult to integrate into a silicon process without affecting the performance of the transistors. Lateral MSM devices with interdigitated fingers on silicon-on-insulator (SOI) substrates offer similar tradeoff between bandwidth and efficiency [7], while recent demonstrations of lateral trench MSMs offer enhanced performance [8].

Resonant cavity PIN photodiodes have been demonstrated with high bandwidth (>34GHz) and good quantum efficiency (42%) at low bias voltages [9,10]. The primary drawback of this design is the low quantum efficiency at non-resonant wavelengths of the cavity. Finally, fully CMOS compatible photodetectors with no process modifications have been reported using spatially modulated approach [11] or using the well/substrate PN junction as a screening terminal [12]. While these approaches show promise, the bandwidths reported to date are limited to 1Gb/s.

Lateral Surface PIN Photodiode

Figure 3. Lateral surface PIN photodiode. The n-type and p-type fingers are formed during the source and drain implants during the CMOS process.

Our approach is to construct lateral PIN photodiodes that are relatively easy to incorporate into the silicon CMOS process. The surface PIN photodetector shown in Figure 3 is a good candidate. Since the n-type and p-type electrodes are formed at the surface of the device, the device can be fabricated in an unmodified CMOS process by creating the interdigitated fingers during the same fabrication steps used to form the source and drain of the CMOS transistor structures. The electric field intensity is high at the surface of the device and decreases at lower depths into the silicon substrate, and carriers generated deep beneath the surface drift slowly to the contacts, limiting the speed. The device can be placed on an SOI substrate to block these slow carriers, and this typically limits the absorption region thickness to ~2.0mm or less to achieve bandwidths up to a few GHz. The incorporation of the buried oxide also forms a resonant-cavity structure due to reflections at the air-Si and Si-SiO₂ interfaces. This resonant cavity can increase the low quantum efficiency caused by the relatively thin absorption region. In addition, these lateral PIN structures often exhibit avalanche gain [13,14], which can greatly enhance the efficiency due to the superior ionization ratio of electrons and holes in silicon. One drawback to this device is that the bandwidth is a strong function of the applied bias voltage, since the electric field is not uniform throughout the device.

Recently, we demonstrated a monolithic silicon receiver in a 130nm CMOS process using this lateral surface PIN structure [15]. A 50mm x 50mm photodiode with a finger width and spacing of 0.5mm and 1.0mm, respectively, was monolithically integrated with a 3-stage CMOS transimpedance amplifier (TIA). At a wavelength of 850nm, the receiver achieved a sensitivity of -10.9dBm (BER=10^-9) at 5.0Gb/s and operated error free up to 8.0Gb/s. This performance was obtained at a drain voltage (V_DD) of 3.2V and a PD voltage of 24V. Single supply (V_DD=V_PD) operation at 3.0V was achieved up to a data rate of 3.125Gb/s.

Figure 4. Eye diagram at 10Gb/s of lateral surface PIN detector and SiGe transimpedance amplifier.

The bandwidth of the PD was 8.0GHz and the peak quantum efficiency was 12% [16]. Since the overall limitation on the bit rate of the receiver was determined by the bandwidth of the TIA, a discrete SOI PD was wire bonded to a high speed SiGe transimpedance amplifier to demonstrate this PD structure at higher speeds [14]. This receiver achieved a BER of 10^-9 at 10Gb/s at an incident optical power of -6.9dBm. The receiver operated error-free up to 11Gb/s, which is the highest speed ever reported for an all-silicon optical receiver. The PD exhibited an avalanche gain near 4 at its operating voltage of -28V. The eye diagram at 10Gb/s is shown in Figure 4.

Lateral Trench Detector

Figure 5. Lateral trench detector (LTD). The 0.4mm wide by 8.0mm deep trenches extend the absorbtion length while maintaining a uniform electric field between the trenches, enabling efficient, low voltage operation.

Other than the substrate, the fabrication steps in creating a lateral surface PIN device are identical to a standard CMOS process. With the addition of a slightly more process complexity, the lateral trench detector (LTD) shown in Figures 5 and 6 can be formed. This process is a modification of the process used to form deep trench DRAM capacitors. The trenches with high aspect ratios (0.4mm wide by 8.0mm deep) are formed using reactive ion etching. The trenches are then filled alternatively with n-type and p-type polysilicon to create the lateral PIN structure. In this device, the absorption length is decoupled from the carrier transit time while maintaining a uniform electric field between the trenches. This enables high-speed, efficient operation at low bias voltages.

Figure 6. Scanning elctron image of an LTD on SOI prior to filling the n+ trenches. The p+ trenches have been filled with a sacrificial BSG layer to mask the n+ deposition.

Large area (75mm diameter) LTDs with a finger spacing of 3.3mm were fabricated on bulk and SOI substrates [17]. At 850nm, the bulk and SOI devices achieved quantum efficiencies of 68% and 51%, respectively, as shown in Figure 7. The cavity resonance created by the buried oxide is evident in the SOI device. This wavelength dependency can be negated by proper choice of buried oxide layer thickness as well as by using an anti-reflecting coating on the detector surface. The SOI LTD exhibited a pulse width of 82ps (Figure 8) and bandwidth over 2GHz at a reverse bias of 4.0V, while a low frequency tail was evident in the LTD fabricated on the bulk substrate. This tail, caused by the slowly drifting carriers generated below the trenches, limited the -3dB bandwidth to less than 1GHz. Nevertheless, the pulse width of 92ps at indicated that high bit rate operation was possible.

Figure 7. External quantum efficiency of LTD on bulk and SOI substrates. Note that thebulk efficiency includes carriers generated underneath the trenches.

Since only discrete devices were fabricated, the bulk substrate LTD was wire bonded to a SiGe TIA to form a silicon optical receiver [18]. This receiver achieved a sensitivity of -17.1dBm at 2.5Gb/s, -11.0dBm at 5.0Gb/s and operated error free up to 6.5Gb/s, all at a single supply voltage of only 3.3V. Even better performance is expected as the device dimensions are scaled for higher speed operation.

Figure 8. Pulse response at 850nm of LTDs on bulk and SOI substrates at -4V. A tail is observed in the bulk device, caused by carriers generated beneath the 8mm deep trenches.

Figure 9. Sensitivity versus data rate for silicon optical receivers formed with lateral PIN photodiodes.

Conclusions

Monolithic silicon receivers are attractive candidates for parallel transceiver arrays. We have demonstrated two lateral PIN photodiode structures compatible with silicon CMOS technology that offer high performance at high bit rates. The lateral surface PIN device, which can be integrated in an unmodified CMOS process by using an SOI substrate, features high speed, low capacitance and reasonable efficiency, and the performance improves at elevated operating voltages. The lateral trench detector (LTD), which is compatible with a modified EDRAM CMOS process, is capable of high speed, efficient operation at low operating voltages.

Acknowledgements

The authors wish to thank those who made contributions to this work, including W. E. Wu, Ken Rim, Daniel Kuchta, Steven Zier, and Michael Sorna.

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