I. Introduction
The enormous growth of Internet traffic in recent years has led to a dramatic increase in demand for data transmission capacity. Previously, network backbone capacity has been dominated by voice traffic. Today, data traffic capacity requirements are beginning to surpass those for voice. In anticipation of this added demand, the telecommunications industry is actively working to increase the transmission capacity available in backbone networks. Recent advancements in backbone network capacity can be credited, in large part, to developments in high-speed transmission and switching systems. Of particular importance in the transmission arena has been the emergence of wavelength division multiplexing (WDM) technology, which supports multiple simultaneous wavelength channels on a single fiber. Another promising transmission technology, still in its infancy commercially, is optical time division multiplexing (OTDM), which supports ultrafast data rates (i.e. > 100 Gbit/s) on a single wavelength channel. Both WDM and OTDM systems with point-to-point transmission capacity exceeding a Tbit/s have been demonstrated recently in the laboratory [1]-[3]. Such high data rates will place severe demands on network element processing speeds. Additionally, optical-electronic-optical (O/E/O) conversion in electronic routers will result in congestion and reduced efficiency in WDM and OTDM optical networks.

II. Ultrafast Optical Packet Switch
Optical routers in future packet-switched networks will allow active packet routing within and between wavelengths while simultaneously providing an optical path that is transparent to both data format and transmission rate. All-optical packet-switched networks are expected to provide many advantages compared to earlier architectures. First, low-level network functionality, such as routing, is distributed in the optical network core, while high-level functionality, like traffic grooming and protocol translation which requires a large amount of slow processing, is pushed to the network edges. Because payload data is transparent in an optical packet-switched network, each switch can remain in any given state for an arbitrary amount of time and a wide range of services from best-effort datagram, to virtual circuit connections, to guaranteed bandwidth via a dedicated lightpath can be provided simultaneously. Optical packet-switched networks may also provide scalability and flexibility to efficiently handle time-dependent network traffic patterns.

Figure 1 – Generalized 16x16 optical packet switch architecture consists of an input interface, header processor, switching matrix, and output matrix.

Here, we present a possible architecture for a 16x16 optical packet switch based on ultrafast serial processing achievable with ultrafast Boolean optical logic gates. A generalized optical packet switch [4],[5] consists of an input interface, header processor, switching matrix, and output interface as shown in Figure 1. The input interface provides synchronization for packet delineation and phase alignment at the switching matrix input. The header processor reads the packet header and provides the signals used to configure the switching matrix. The switching matrix routes the packet to the desired port and resolves port contention. The output interface performs packet regeneration and synchronization to provide high-quality transmission to the next node in the network.

The packet architecture is an important feature for ultrafast optical packet-switched networks. We will consider a fixed-length optical packet architecture demonstrated previously by our group for use in a slotted OTDM network testbed that is capable of operating at line rates of 112.5 Gbit/s [6]. In this demonstration, a single optical packet is 100 ns long and fully-loaded with synchronous 12.5 GHz network clock pulses interleaved between 100 Gbit/s rate multiple-bit address header and payload data. The first clock pulse in each packet is removed to provide a packet marker. In order to achieve packet switching at rates beyond 100 Gbit/s, the packet marker is used to synchronize the packet at the network interface and the address header is optically processed for routing information used to forward the packet through the all-optical switching matrix.

Figure 2 – The input interface consists of an optical clock source, bit synchronizer, counter, and packet synchronizer. Fine and coarse packet synchronization is achieved with an ultrafast optical NAND gate contained in the bit synchronizer.

At the packet switch input and output interfaces, both fine and coarse packet synchronization are required. Fine synchronization is achieved at each input port using a single all-optical logic gate. In this case, the optical NAND gate performs a bitwise comparison between the global clock pulses in the network packet and clock pulses generated locally in the input interface. Because the optical logic gate is biased for NAND operation, a single synchronization pulse is switched out of the gate only when the missing packet marker pulse is present in the network packet. The packet marker can be used for both fine and coarse packet synchronization at the packet switch input interface as shown in Figure 2. In order to achieve fine synchronization, the synchronization pulse is used in conjunction with an optoelectronic dithering phase-locked loop to maintain the temporal overlap of the optical pulses in the locally generated clock train with the global clock pulses in the network packet. Coarse packet synchronization can be achieved if the synchronization pulse arrival time for each input port is measured via a counter and then compensated using a variable optical delay line on each input port. As shown in Figure 2, each packet can be temporally aligned prior to entering the switch matrix after fine- and coarse-synchronization at the packet switch input interface. In our proposed 16x16 packet switch architecture, synchronization at the input and output interfaces can be achieved with 16 optical logic gates.

The 16x16 switching matrix consists of an input queued Banyan configuration. An NxN Banyan network implemented using interconnected 2x2 switches offers advantages of relatively low switch count (0.5Nlog₂N) and straightforward address header processing (see for example [7]). Another key advantage that can be realized if the Banyan matrix is composed of ultrafast optical 2x2 switches [8] is picosecond reconfiguration times. In this example, our 16x16 Banyan switch matrix will require 32 interconnected 2x2 optical switches and each path length must be closely matched in order to maintain packet synchronization. Monolithic integration is one potentially viable means of meeting this precise interconnection requirement.

A requirement of the input buffer queue is that it provides complete packet contention resolution prior to the Banyan switch matrix. Most optical buffers proposed today require fiber delay lines and storage time variability is provided using the temporal, spatial, or wavelength domain (see for example [9]-[11]). Although head-of-line blocking in an input queued packet switch has been shown to limit throughput to 58.6% [12], it is possible to use virtual output queueing via more complex input buffer queue architectures to achieve 100% contention resolution [13],[14]. If port contention is completely resolved prior to the Banyan switch matrix, this condition will significantly reduce the logic density required in the header processing block of our proposed optical packet switch.

Header processing can be implemented with ultrafast optical logic gates to minimize propagation delays through the packet switch and allow serial processing at line rates beyond the abilities of available electronics. Because current optical logic gate technology cannot easily provide the complex processing and high level of integration achieved by the electronics industry, special care must be taken to simplify the header processing procedure in an optical packet switch. A single optical AND gate has been demonstrated for processing multiple-bit address headers at >100 Gbit/s line rates [6]. In this experiment, the optical AND gate performed a bitwise comparison of 4-bit network and local receiver address headers with no restrictions on the allowable keyword space. The 16x16 Banyan switch proposed in this paper consists of 4 columns each composed of 8 ultrafast 2x2 switches and each packet header contains 4 address bits. In a Banyan matrix, only the i^th address must be processed to correctly route the packet through the i^th switch column as shown in Figure 3. The final piece of routing information required is obtained after performing an empty/full check on each packet. If packet contention is completely resolved by the input buffer queue, header processing at each optical 2x2 in the Banyan switch matrix is simplified to just two optical logic gates and a power combiner as shown in Figure 3. In our proposed 16x16 packet switch architecture, header processing can be achieved with 64 optical logic gates.

Figure 3 – Header processor for an ultrafast 2x2 switch in the Banyan matrix. Optical routing information (Ci) is generated for the ith column of the Banyan matrix by comparing the ith header bit in packet 1 (A1i) and packet 2 (A2i) with the empty/full check bit for packet 1 (E1i).

III. Conclusion
All-optical packet switching will be required to eliminate the O/E/O conversion bottlenecks that limit capacity growth in today’s networks. One potential means of implementing a 16x16 all-optical packet switch is to exploit the ultrafast serial processing provided by optical logic gates and memory buffers. We have presented a 16x16 optical packet switch architecture that is capable of achieving packet synchronization, header processing, and routing at rates in excess of 100 Gbit/s and requires approximately 100 optical logic gates.

IV. References
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This work was sponsored by the Defense Advanced Research Projects Agency (DARPA) under Air Force contract #F19628-00-C-002. Opinions, interpretations, recommendations, and conclusions are those of the author and are not necessarily endorsed by the United States Government.