OTDM Packet Networking Devices at 100 Gbit/s and Beyond
S. A. Hamilton and B. S. Robinson
Massachusetts Institute of Technology, Lincoln Laboratory, 244 Wood St., Lexington, MA 02420
Telephone: (781) 981-2904, Fax: (781) 981-4129, Email: email@example.com
II. Ultrafast Optical Packet Switch
Here, we present a possible architecture for a 16x16 optical packet
switch based on ultrafast serial processing achievable with ultrafast
Boolean optical logic gates. A generalized optical packet switch ,
consists of an input interface, header processor, switching matrix,
and output interface as shown in Figure 1. The input interface provides
synchronization for packet delineation and phase alignment at the switching
matrix input. The header processor reads the packet header and provides
the signals used to configure the switching matrix. The switching matrix
routes the packet to the desired port and resolves port contention.
The output interface performs packet regeneration and synchronization
to provide high-quality transmission to the next node in the network.
The packet architecture is an important feature for ultrafast optical
packet-switched networks. We will consider a fixed-length optical packet
architecture demonstrated previously by our group for use in a slotted
OTDM network testbed that is capable of operating at line rates of 112.5
Gbit/s . In this demonstration, a single optical packet is 100 ns
long and fully-loaded with synchronous 12.5 GHz network clock pulses
interleaved between 100 Gbit/s rate multiple-bit address header and
payload data. The first clock pulse in each packet is removed to provide
a packet marker. In order to achieve packet switching at rates beyond
100 Gbit/s, the packet marker is used to synchronize the packet at the
network interface and the address header is optically processed for
routing information used to forward the packet through the all-optical
At the packet switch input and output interfaces, both fine and coarse
packet synchronization are required. Fine synchronization is achieved
at each input port using a single all-optical logic gate. In this case,
the optical NAND gate performs a bitwise comparison between the global
clock pulses in the network packet and clock pulses generated locally
in the input interface. Because the optical logic gate is biased for
NAND operation, a single synchronization pulse is switched out of the
gate only when the missing packet marker pulse is present in the network
packet. The packet marker can be used for both fine and coarse packet
synchronization at the packet switch input interface as shown in Figure
2. In order to achieve fine synchronization, the synchronization pulse
is used in conjunction with an optoelectronic dithering phase-locked
loop to maintain the temporal overlap of the optical pulses in the locally
generated clock train with the global clock pulses in the network packet.
Coarse packet synchronization can be achieved if the synchronization
pulse arrival time for each input port is measured via a counter and
then compensated using a variable optical delay line on each input port.
As shown in Figure 2, each packet can be temporally aligned prior to
entering the switch matrix after fine- and coarse-synchronization at
the packet switch input interface. In our proposed 16x16 packet switch
architecture, synchronization at the input and output interfaces can
be achieved with 16 optical logic gates.
The 16x16 switching matrix consists of an input queued Banyan configuration.
An NxN Banyan network implemented using interconnected 2x2 switches
offers advantages of relatively low switch count (0.5Nlog2N)
and straightforward address header processing (see for example ).
Another key advantage that can be realized if the Banyan matrix is composed
of ultrafast optical 2x2 switches  is picosecond reconfiguration
times. In this example, our 16x16 Banyan switch matrix will require
32 interconnected 2x2 optical switches and each path length must be
closely matched in order to maintain packet synchronization. Monolithic
integration is one potentially viable means of meeting this precise
A requirement of the input buffer queue is that it provides complete
packet contention resolution prior to the Banyan switch matrix. Most
optical buffers proposed today require fiber delay lines and storage
time variability is provided using the temporal, spatial, or wavelength
domain (see for example -). Although head-of-line blocking in
an input queued packet switch has been shown to limit throughput to
58.6% , it is possible to use virtual output queueing via more complex
input buffer queue architectures to achieve 100% contention resolution
,. If port contention is completely resolved prior to the Banyan
switch matrix, this condition will significantly reduce the logic density
required in the header processing block of our proposed optical packet
Header processing can be implemented with ultrafast optical logic gates
to minimize propagation delays through the packet switch and allow serial
processing at line rates beyond the abilities of available electronics.
Because current optical logic gate technology cannot easily provide
the complex processing and high level of integration achieved by the
electronics industry, special care must be taken to simplify the header
processing procedure in an optical packet switch. A single optical AND
gate has been demonstrated for processing multiple-bit address headers
at >100 Gbit/s line rates . In this experiment, the optical AND
gate performed a bitwise comparison of 4-bit network and local receiver
address headers with no restrictions on the allowable keyword space.
The 16x16 Banyan switch proposed in this paper consists of 4 columns
each composed of 8 ultrafast 2x2 switches and each packet header contains
4 address bits. In a Banyan matrix, only the ith address
must be processed to correctly route the packet through the ith
switch column as shown in Figure 3. The final piece of routing information
required is obtained after performing an empty/full check on each packet.
If packet contention is completely resolved by the input buffer queue,
header processing at each optical 2x2 in the Banyan switch matrix is
simplified to just two optical logic gates and a power combiner as shown
in Figure 3. In our proposed 16x16 packet switch architecture, header
processing can be achieved with 64 optical logic gates.
2. S. Bigo, Y. Frignac,G. Charlet, W. Idler, S. Borne, H. Gross, R.
Dischler, W. Poehlmann, P. Tran, C. Simmoneau, D. Bayart, G. Veith,
A. Jourdan, J.-P. Hamaide, 10.2 Tbit/s (256x42.7 Gbit/s PDM/WDM)
transmission over 100 km TeraLight fiber with 1.28 bits/s/Hz spectral
efficiency, in Optical Fiber Communications Conference,
Anaheim, CA, PD25 (2001).
3. M. Nakazawa, T. Yamamoto, and K. R. Tamura, 1.28 Tbit/s-70
km OTDM transmission using third- and fourth-order simultaneous dispersion
compensation with a phase modulator, Electron. Lett., 36,
4. D. J. Blumenthal, P. R. Prucnal, and J. R. Sauer, Photonic
packet switches: architectures and experimental implementations,
Proc. IEEE, 82, 1650-1667 (1994).
5. S. L Danielsen, P. B. Hansen, and K. E. Stubkjaer, Wavelength
conversion in optical packet switching, J. Lightwave Technol.,
16, 2095-2108 (1998).
6. S. A. Hamilton and B. S. Robinson, 100 Gbit/s synchronous
all-optical time-division multiplexing multi-access network testbed,
in Optical Fiber Communications Conference, Anaheim, CA, ThEE3
7. P. R. Prucnal, Optically processed self-routing, synchronization,
and contention resolution for 1-D and 2-D photonic switching applications,
IEEE J. Quantum Electron., 29, 600-612 (1993).
8. G. Theophilopoulos, M. Kalyvas, C. Bintjas, N. Pleros, K. Yiannopoulos,
A. Stavdas, H. Avramopoulos, and G. Guekos, Optically addressable
2x2 exchange/bypass packet switch, IEEE Photon. Technol. Lett.,
14, 998-1000 (2002).
9. J. D. Moores, W. S. Wong, and K. L. Hall, 50-Gbit/s optical
pulse storage ring using novel rational-harmonic modulation, Opt.
Lett., 20, 2547-2549 (1995).
10. D. K. Hunter, M. C. Chia, and I. Andonovic, Buffering in
optical packet switches, J. Lightwave Technol., 16, 2081-2094
11. D. K. Hunter, et. al., WASPNET: a wavelength switched packet
network, IEEE Commun. Mag., 120-129 (1999).
12. M. J. Karol, M. G. Hluchyj, S. P. Morgan, Input versus output
queueing on a space-division packet switch, IEEE Trans. Commun.,
35, 1347-1356 (1987).
13. N. McKeown, A. Mekkittikul, V. Anantharam, and J. Walrand, Achieving
100% throughput in an input-queued switch, IEEE Trans. Commun.,
47, 1260-1267 (1999).
14. G. Thomas, Multi-channel input-queueing for high throughput switches, Electron. Lett., 33, 184-185 (1997).
This work was sponsored by the Defense Advanced Research Projects Agency (DARPA) under Air Force contract #F19628-00-C-002. Opinions, interpretations, recommendations, and conclusions are those of the author and are not necessarily endorsed by the United States Government.